We are to add more functionality to the Skeletal Processor created in the Laboratory 2A. The following Skeletal Processor should read (load) 16 bit machine language instructions to MBR, memory buffer register) from the memory, a PROM, at the location pointed by PC and transfer the contents of MBR to the Instrucyion Register, IR, in the subcycle SC2. Click the red framed boxes to see sample design of new required units.

(1) Create a PROM containing a number of 16 bit patterns as follows.

(2)
Attach IR, a 16 bit Instruction Register. Wire the LOAD control port of IR to SC2 line so that the transfer of the contents of MBR is done in the subcycle SC2.

(3)
Attach a 4X16 Decoder, Machine Instruction (OP Code) Decoder, to IR as shown below. Wire the output line 0 (HLT) of the Decoder to the HALT input line of the RUN flip-flop. When your processor executes the instruction "0xxx"(Hex), OPcode HLT, the output from the RUN flip-flop should drop to 0, thus halting the clock signal.

(4)	Submit your successful Skeletal Processor 2 design (relevant .CCT files) to Dr. Hasegawa by Wednesday, February 18, 10:00pm   Note: You could submit a partial solution (without a durable RUN flip-flop).