(1)
Load the following CAPC Processor 2 created in Lab6/7.
(2) Wire the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC3, Subcycle 3
of the Clock, to the Send line of Zero and Buffer12 (of IR register).
(3) Extend the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC3, Subcycle 3
of the Clock, to the Load line of MAR, Memory Address Register.
(4) Wire the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC4, Subcycle 4
of the Clock, to the Send line of Greg, G register.
(5) Extend the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC4, Subcycle 4
of the Clock, to the Load line of MBR2, Memory (Input) Buffer Register. Extend further the line
to the Send line of MBR2 and then to NOT(/WE) line of the RAM.
(6) Store manually the following test program in RAM.
