In this Lab3 we will be attaching 4K RAM unit, based on a simulator provided by LogicWorks 4, to the circuits created in Lab2.

(0) (added - Feb8, 2002) First create a 2x2 RAM device (4 address 2-bit memory) as follows:
(0a) Open the PROM/RAM/PLA Wizard module by clicking on its button (chip shape), the second button on the right side of the top tool bar.
(0b) Select the RAM device to build option and click the Next button.
(0c) Enter the parameters required for this RAM as follows:

Options	Specification
Address Lines	2
Chip Enables	0
Bits per Word	2
Single Word Simulation	check
Common I/O pins	check
3-state Outputs
Output Enable Pin	check

(0d) Enter the name "RAM2x2" for the new part and the name "CAPCRams" for the destination library and click the New Lib button.
(0e) Click the Finish button to save the completed part.
(0f) Select RAM2x2 from the Library window and place it on the design sheet.
(0g) Select Binary Switch from Library window and place 7 copies, 4 on the left hand side, 2 on the right, and 1 at the top of RAM2x2.
(0h) Attach Binary switches to NOT(OE), NOT(WE), A0, and A1.
(0i) Select 3-state Buffer from the Library window and make 2 copies. Attach DIO0 and DIO1 to their output lines.
(0j) Attach 2 Binary Switches to input lines of 3-state Buffers.
(0k) Attach 1 Binary Switch to the control lines of two 3-state Buffers.
(0l) Select Binary Probe and place 2 copies on the design space. Connect them to DIO0 and DIO1. Note that DIOxes are bi-directional.
(0m) Start experimentation. Configure Binary Switches as follows: 10 to A0 and A1 (address 2); 0 to NOT(WE) and 1 to NOT(OE) (Write to Memory mode); 01 to DIO0 and DIO1 and 0 to the control line of 3-state Buffers (Enter data 01 to Ram2x2).
(0n) Read the memory as follows: 1 to NOT(WE) and 0 to NOT(OE) (Read from Memory mode); 10 to A0 and A1 (address 2); 1 to the control line of 3-state Buffers (disconnect input lines); and read the data at address 2 through Binary Probes (they should display 01).

(1) Now create a 4K RAM device (simulator) as follows:
(1a) Open the PROM/RAM/PLA Wizard module by clicking on its button (chip shape), the second button on the right side of the top tool bar.
(1b) Select the RAM device to build option and click the Next button.
(1c) Enter the parameters required for this RAM as follows:

Options	Specification
Address Lines	12
Chip Enables
Bits per Word	16
Single Word Simulation	check
Common I/O pins	check
3-state Outputs
Output Enable Pin	check

(1d) Enter the name "RAM12x16" for the new part and the name "CAPCRams" for the destination library and click the New Lib button.
(1e) Click the Finish button to save the completed part.

(2a) Now download "lab2.cct" file in the design space of LogicWorks4. Modify those registers, A and B, as 12-bit registers (use lower 12 bits of 16-bit Bus). Rename them as PC, program Counter, and MAR, memory address register.
(2b) Create one 16-bit register, name it as IR, Instruction Register, and attach it to the Bus (as in Lab2).

(3a) Select RAM12x16, created in (1), from the Library window and place it near MAR.
(3b)(Re)Attach 12 output lines of MAR directly to 12 Address (Input) lines, A0 to A11, of RAM12x16.
(3c)(Re)Name the clock line, LOAD_MAR, of MAR as (Read)ToMAR line. It will be activated by a "...->MAR" signal.

(4) 16-bit MBR register, Memory Buffer Register, (or MD) plays dual role of an interface to RAM12x16, as both input source (in Write mode) and output destination (in Output mode).
(4a) Create a 16-bit register, name it as MBR and place it near RAM12x16. Attach MBR tentatively to the Bus as in Lab2.
(4b) Now we are going to attach RAM12x16 to MBR. That is, we have to attach another 16-bit Data (input) source to MBR. (Note that D0..D15 of MBR are connected to the Bus.) Use MUX chips to connect 16 data lines, D0..D15, of RAM12x16 to 16 input lines,D0..D15, of MBR. The default value (0) of the control line of this MUX should connect RAM12x16 to MBR.
(4c) Use DeMUX chips (or a number of AND gates with one control line) to splice 16 output lines (Qes) of MBR and become the source (input lines) of RAM12x16. The default value (0) of the control line of this DeMUX should connect MBR to the Bus.

(5) The following experiment will simulate a Fetch cycle of our processor CAPC. (Ignore the operation PC<-PC+1 and related registers X and Y of ALU, that is, a part of T1 and T3 for now.)
(5a) Place binary number "0000 0100 0110" (046h) in PC. This is the address of next instruction to be executed.
(5b) Use Binary Switches for A0..11, D0..15, and /W to store the machine instruction "0001 0010 1000 1011" (ADD [28Bh]) at the location 046h of RAM12x16.
(5c) Connect T0, T1 and T5 of Fetch cycle to the LOAD_XXX (clock) line and Send_XXX line (connect register XXX line of 3-state device) of each pertinent register (PC, MAR, MBR, and IR).
(5d) Observe, after one Fetch cycle, the machine instruction "0001 0010 1000 1011" is safely stored in IR register.

Submit entire "Lab3.cct" file via FTP to each group Web space by 10.00pm on Saturday, February 16th.