Lab 7: Hardware Interrupt
The final piece of the puzzle is now to be studied: Interrupt.
The prime purpose of interrupt is to provide instantaneous communication
between the processor, CAPC, and other interfaces which serve external devices.
Typically, when a external device (such as keyboard) needs service from the
processor, it pulls down INT line (normal state is high(1)) of the processor
(via another chip called Programmable Interrupt Controller such as Intel8259).
In this design of Interrupt circuits, we try to present a simple prototype, rather
than a full-fledged Interrupt system.
(0) Make a complete copy of your CAPC processor.
(1) Open LW4 and load the copy in (0) on the design sheet.
(2) Place a copy of 12 bit register on the design sheet and name it as INTR(egister).
(3) Select D-(or JK-)type Flip-Flop and place it near the RUN Flip-Flop.
Name the Flip-Flop as INT(errupt) Flip-Flop. This pair, INT Flip-Flop and INTR in (2)
will be used by the Programmable Interrupt Controller (external chip). The PIC will
flag (INT is set to 1) and place the identification number (such as 000Hex for a Keyboard)
of the external device which requested processor's service to the INTR register.
(3a) The Clock-pin and D-(or JK- tied together)pin are to be connected with an
Interrupt Controller chip (for now, attach a Binary Switch).
(4) Fill in the Interrupt Vector (@000Hex) for
Interrupt 0 (INT0-Keyboard Interrupt):
(5) Design and write a simple Keyboard Interrupt Handler such as:
(6) Load the Interrupt Vector for Int0 (Keyboard Interrupt) in (4) to RAM memory at address
000Hex and the Keyboard Interrupt Handler in (5) to RAM memory at address 200Hex.
(7) Simulate and test the Interrupt circuits manually as follows:
The CAPC processor uses RAM locations, 000-010, as Interrupt Vectors, each location
contains an instruction "jmp location_for_interrupt_service_handler" for the corresponding
external device.
(3b) The output line, Q, of INT Flip-Flip is called INT line.
The logic of INT line is as follows:
(3b0) If CAPC is in Halt state (RUN Flip-Flop is off(0)), then nothing happens
under either condition INT=0 or INT=1.
In the following, assume RUN Flip-Flop is set (1).
(3b1) NEG(INT) line will be ANDed with T0-T7 lines with no change in the current
circuit design, that is, the processor CAPC continues to run.
The logic is:
(INT=0, T0, Fetch)=(T0, Fetch); ... ;(INT=0, T7, Fetch)=(T7, Fetch);
(INT=0, T0, Execute)=(T0, Execute); ... ; (INT=0, T7, Execute)=(T7, Execute).
(3b2) The INT line will be ANDed with clock lines, T0-T7, and create
To-T7 with Fetch line and INT line according to the following logic:
(3b2a) (INT=1, T0, Execute)=(T0, Execute); ... ; (INT=1, T7, Execute)=(T7, Execute).
(3b2b) If (INT=1, T0=1, Fetch=1), then copy the (return) address in PC to G.
(2b2c) If (INT=1, T2=1, Fetch=1), then copy the contents of INTR(egister) to MAR.
(2b2d) If (INT=1, T5=1, Fetch=1), then activate Output/Enable and copy MBR to IR.
(2b2e) If (INT=1, T7=1, Fetch=1), then clear INT Flip-Flop (INT=0).
Mem Loc Assembly Machine Code
Description 000 jmp 200 1010 0010 0000 0000
jmp to the (Keyboard) Interrupt 0 Handler located at 200Hex
Mem Loc Assembly Machine Code
Description 200 sdg [100] 0111 0001 0000 0000
Start INT0 Handler:Save G (return address) to the memory @100Hex 201 ktg 1110 0000 0000 0000
Store key entry in KB register to G 202 sdg [101] 0111 0001 0000 0001
Save G (key entry) to the memory @101Hex 203 inj [100] 0110 0001 0000 0000
Jump to the return address, stored in the memory @100Hex
(7a) Write a program which loops permanently and load it in the memory at the address 300Hex:
Mem Loc Assembly Machine Code
Description 300 nop 1111 0000 0000 0000
No operation 301 jmp 300 1010 0011 0000 0000
jmp back to the above address at 300Hex
(7b) Execute the program (7a) by manually inserting 300Hex in PC(or executing "jmp 300").
(7c) Enter 16 bit data ("A09D"Hex) from Keyboard as in Lab 5.
(7d) Manually enter 000Hex in INTR register.
(7e) Manually set INT Flip-Flop to 1.
(7f) Observe CAPC automatically captures Key Entry "A09D" in the memory located at 100Hex.
Submit your "lab7.cct" file (or FTP it to your Web space and notify) via eMail to Dr. Hasegawa by 10:00pm Saturday, March 23rd.