In general, upper 4 bits of Machine Instruction are assigned to an OP(eration)
code and lower 12-bits the Operand which points to a location of the memory.
Here we look at "LDG [Address]" (Load G register) instruction in detail.
Machine Instruction:
0110
0111 1010 0001
Assembly Instruction:
LDG
[7A1h]
Description:
Load G Register with
the contents of memory at 7A1(hex)
The sequence of operations to be performed in Execution Cycle:
Note: A modification (*)-(**) is made to implement our circuits in LogicWorks4.
(*) Remove this signal and move it here (**).
Subcycle
HDL
Note T7 in Fetch Cycle E_CYCLE Set State Flip-Flop to Execute(1) T0 MAR<-IR[0..11] copy IR(D0..11) to MAR T1 (*)[READ_MEM] (*)[activate READ_MEM] T2 T3 T4 (*)[Strobe to MBR] (*)[MBR Ready] T5 (**)[Output/Enable,]G<-MBR (**)[activate Output/Enable,]Load MBR to G T6 T7 F_CYCLE Reset State Flip-Flop to 0(F_CYCLE)