Click Description column for details. (Modified March 4; Modified March 11, 2002)

OP Code	Assembly Code	Operand(Address)	Description
0000	HLT	ignored	Halt the machine
0001	ADD	xxxxxxxxxxxx	Add [Operand] to G
0010	XOR	xxxxxxxxxxxx	ExOr G with [Operand]
0011	AND	xxxxxxxxxxxx	AND G with [Operand]
0100	LOR	xxxxxxxxxxxx	OR G with [Operand]
0101	NOT	ignored	NOT(G) to G
0110	LDG	xxxxxxxxxxxx	Load [Operand] to G
0111	SDG	xxxxxxxxxxxx	Send G to [Operand]
1000	SRJ	xxxxxxxxxxxx	Subroutine Jump
1001	JMI	xxxxxxxxxxxx	Jump if G[15] is set(1)
1010	JMP	xxxxxxxxxxxx	Unconditional Jump
1011	INJ	xxxxxxxxxxxx	Indirect Jump
1100	INT	yyyyyyyyxxxx	(Software) Interrupt
1101	ROL	ignored	Rotate G one bit to left
1110	KTG	ignored	Keyboard to G
1111	NOP	ignored	No Operation

CAPC Processor Fetch Cycle

For simplicity, our 16-bit processor CAPC has only one bus. With our CLOCK generator designed in Lab1 running, the first and regular operation is that of Fetch: Note: A modification (*)-(**) is made to implement our circuits in LogicWorks4. (*) Remove this signal and move it here (**).
Subcycle	HDL	Note
T0	MAR<-PC, X<-PC	copy PC to MAR, X
T1	Y<-1 (*)[, READ_MEM]	copy 1 to Y(*)[, Activate READ_MEM]
T2
T3	PC<-X+Y	copy X+Y (PC+1) in ALU to PC
T4
T5	(**)[Output/Enable,]IR<-MBR	(**)[Activate Output/Enable,] copy MBR to IR
T6
T7