In general, upper 4 bits of Machine Instruction are assigned to an OP(eration)
code and lower 12-bits the Operand which points to a location of the memory.
Here we look at "SDG [Address]" (Send G register) instruction in detail.
Machine Instruction:
0111
1001 1101 0000
Assembly Instruction:
SDG
[9D0h]
Description:
Copy(Send) the contents of G Register to
the contents of memory at 9D0(hex)
The sequence of operations to be performed in Execution Cycle:
Note: A modification (*)-(**) is made to implement our circuits in LogicWorks4.
(*) Remove this signal and move it here (**).
Subcycle
HDL
Note T7 in Fetch Cycle E_CYCLE Set State Flip-Flop to Execute(1) T0 MAR<-IR[0..11] copy IR(D0..11) to MAR T1 T2 T3 T4 (*)[WRITE_MEM] (*)[initiate WRITE_MEM] T5 (**)[Write/Enable,]MBR<-G (**)[activate Write/Enable,]Load G to MBR T6 T7 F_CYCLE Reset State Flip-Flop to 0(F_CYCLE)