In this experiment, you are required to design and implement a skeletal processor which updates 12 bit MAR, Memory Address Register, by copying the contents of another 12 bit register PC, Program Counter, via the main 16 bit bus. The transfer from PC to MAR must be done in the first subcycle, SC0. The following is an example circuit design:
STEP	DESCRIPTION
1	Design/Build a generic 12 bit register (with 3 state SEND line) in LW4. Use a copy of Reg-8 ( 8-bit register) , a copy of Reg-4 ( 4 bit register), a Buffer-8TS (3 state 8-bit buffer), and a Buffer-8TS (3 state 8-bit buffer) in the tool box for simplicity. The register must have 12 (D0..D11) data input lines, a load clock line, a (3 state) send, a clear (Reset) line, and 12 (Q0..Q11) output lines. Use a copy of this generic register, R12t, to create 12 bit register MAR.
2	The required Skeletal Processor will be build by combining a Clock Unit, and MAR, connected via 16 bit main Bus, as is shown in the Figure 1.
3	Submit your successful Skeletal Processor Step 1 design (relevant .CCT files) to Dr. Hasegawa by Jan.30th, 10:00pm