(1)
Load the following Base Processor created in Lab4. Then attach a generic 4X16 decoder, mach, and 12 bit (3 stated) buffer, b12, as follows.
Attach also a 4 bit Zero unit, z4, with Send control line to the upper 4 bit of the 16 bit bus.
(2) We will wire LDG, load G register, instruction as follows.
(2a)First choose a 16 bit register with two control lines, SEND and LOAD,
from your own library. attach it to the right side of the design sheet.
(2b)At the subcycle 3, the machine operation "IR[0..11] -> MAR" and "mem -> MBR" will be wired.
(2b1) Select a AND2 gate from the tool box and wire it with the subcycle 3 line and LDG line (line 6) of the macine
instruction decoder, MACH. The output line of this AND gate, LDG-C3, is to be connected with
SEND line of the IR buffer, IR[0..11], and 4 bit ZERO register.
(2b2) With a delay (3 time unit), connect further the output line of LDG-3C to LOAD port of MAR, memory address register.
With additional delay (3 time unit), extend the output line further and connect to LOAD port of MBR, memory buffer register.
(2c)At the subcycle 4, the machine operation "MBR -> Greg" will be wired.
(2c1) Select a AND2 gate from the tool box and wire it with the subcycle 4 line and LDG line (line 6) of the macine
instruction decoder, MACH. The output line of this AND gate, LDG-C4, is to be connected with
SEND port of the MBR.
(2c2) With a delay (3 time unit), connect further the output line of LDG-3C to LOAD port of Greg.
(3) Test the wiring of LDG.
(3a) Prepare the following machine instructions in NOTEPAD and store it in "LAB6.HEX".
