MicroArchitecture

Introduction  This lecture note is based on Andrew S. Tanenbaum's textbook "Structured Computer Organization" (ISBN 0-13-854662-2) Prentice Hall. I enjoy and admire his style of writing, especially, the chapter on "The Microprogramming Level", for its clarity and depth. My own version of MicroArchitecture (with Lab Exercises) will be published here in this Website at a later date.

Tanenbaum's Processor

The data path  The following shows flow of data between sixteen 16 bit registers, MAR, MBR, 16 bit ALU with a Shifter, A Latch, B Latch and a multiplexer, AMUX, through three data buses, A, B, C.

Click a part of the schematic to have a closer look at data flow control signals.

PC register AC register SP register IR register TIR register Zero register +1 register -1 register AMASK SMASK A register B register C register D register E register F register A Latch B Latch MAR MBR PC register ALU Unit Shifter

Micro Instructions  Micro instructions are designed to control the data flow. Each 32 bit micro instruction defines all the control signals in the above schematic, thus controlling an operation (one complete cycle) of the processor. The data structure of a micro instruction is given by:

Bit3130,29 28,2726,2524 232221 2019,18,17,1615,14,13,12 11,10,9,87,6,5,4,3,2,1,0
SignalAMUXCOND ALUShiftMBR MARRDWR ENCC BusB Bus A BusADDR
0:Alatch0:No jump 0:A+B0:No shift0:No 0:No0:No0:No 0:No
1:MBR1:Jump if N=1 1:A&B1:shift right1:Yes 1:Yes1:Yes1:Yes 1:Yes
2:Jump if Z=1 2:A2:shift left
3:Jump always 3:Not(A)3:(Not used)

COND and ADDR fields will be studied later.