Comp 212 : Computer Design & Architecture II

Hardware Design in LogicWorks 4.0

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Logic Works Libraries


I am keeping two libraries for LogicWorks 4.0 at this point.
Comp211.clf is my library of devices carried over from Comp 211: Computer Design & Architecture I
Comp212.clf is my current working library that I'm adding to as I complete assignments in Comp 212: Computer Design & Architecture II

Hints and Observations

  1. Did you know you can edit the contents of RAM directly? Highlight the ram chip, then from the menu choose
    Options->PROM/RAM/PLA Wizard
    Edit Selected device [NEXT]
    Edit Hex data manually [NEXT]
    It opens a handy little window that lets you view the contents of the ram

Labs Assignments

Lab: Overview:
Current Unstable: Here's my 'current' working skeletal CPU. Download
1 GO The purpose of this lab is to design & build a working CPU clock. It will accept 'ON' and 'HLT' signals.
2 & 2b GO This lab spanned two periods. Here I implemented 16 & 12 bit registers and a PC register that add's 1. Everything is put together and working.
3,4 GO

Machine Decoder, NOP, HLT, and JMP

This lab covered the implementation of the decoder and testing a software coded HLT signal. I also implemented the JMP command to allow the CPU to execute code from other areas of the PROM.
5,6 GO

LDG SDG JMI

Implemented a generic register (GReg). LDG, SDG, JMI are implemented now.
7 GO

PRAM/PROM, ALU

Built the ALU. I've also crafted a custom RAM/PROM device and rebuilt my run ff into a simpler device.
8 & 9 GO

Wiring ALU, Shifter, Interrupt (v.01)

Lab 9 covered in the report for lab 8
Extra
10 GO

Corrected Wiring Interrupt

Lab 10, wiring the interupt asynchronously, is beyond the scope of the course. Possibly coming soon.