COMP 212 - Lab 01: CPU Clock

Introduction:

The preliminary design for a system clock in the 16 bit CPU we are building, will allow for 4 clock cycles for primary operation, plus 4 'processing' cycles for the ALU. The intent of using 8 cycles is to make it easy to implement various ALU operations in the time alloted. Efficiency isn't the primary focus of the design. (yet)

1. There will be two designs for building the sytem clock:

1. use 7 buffers to delay a single clock signal (recommended for simplicity)

2. use a 3 bit counter and a Decoder or MUX to "direct" a clock signal to 8 different outputs

1. The clock will require some method of starting & stopping the system. This will be implemented as a 'run' FlipFlop that can accept 2 inputs: “ON” and “HALT”

Clock Cycle Design 1

• The clock itself starts off with a 10,10 signal. This means it is off for 10 and then on for 10. Setting it to 150,10 gives the desired signal pulse of ________________|^|__

• The 7 buffers are all set to 20

• The total clock cycle is thus 160 units long

• This results in the system being ‘down’ for 150 units when it is first powered on.

Clock Cycle Design 2

• Notes on the counter + MUX method, if I get there.

Run FlipFlop

• There are a few things I would like to see included in the run switch.

1. Asynchronous reset: A CPU should be able to stop the system at any point instead of waiting for the start of the next cycle. This can be better accomplished using Design 2.

2. I/O Switch: A full function 'on/off' switch that can turn the CPU on _and_ off. If the ALU logic fails and a HLT signal can't be generated, another method is required to stop the CPU. Implementing a proper I/O switch will take care of this.