Lab 05 – Greg and LDG SDG

1. GReg

   1. An easy bit of wiring for the GReg out of two 8-bit registers.
   2. Added a line-out (listener) on QF for JMI
   3. Connected the GReg. Tied the instructions from the Machine Decoder with the appropriate clock cycles

2. SDG

   1. Step 1.
      • Mach 7 AND SC3
        << Sends contents IR Operand to BUS
      • + delay
        << Load BUS to MAR
   2. Step 2.
      • Mach 7 AND SC4
        << Send contents GReg to BUS
      • + delay
        << Load BUS to MBR

3. LDG

   1. Step 1.
      • Mach 6 AND SC3
        << Sends contents IR Operand to BUS
      • + delay
        << Load MBR to BUS
   2. Step 2.
      • Mach 6 AND SC4
        << Sends contents MBR to BUS
      • + delay
        << Load BUS to GReg

4. JMI

   1. JMI =
      • Mach 9 AND SC3 AND GReg Q15
        • If GReg Q15 = 1 then
          << Send contents IR Operand to BUS
          
          + delay
          << Load BUS to PCA