Lab 07 – ALU, PRAM/ROM, Encoder

1. Summary

   1. Built ALU.
   2. Wired up a PROM/RAM dual device.
   3. Built an 8 bit encoder for getting clock-cycle names from clock bus.

2. ALU: Algorithm and Logic Unit

   I quickly noticed that this was going to be a repetitive device, so I laid out a basic unit with enough room for all of my future wires. Then it was simply a matter of cloning my drawing, replacing the lower order ALU's with the next version, and running more lines/ ports.

   1. 1 Bit ALU

      • Started by Building your Basic 1 bit ALU
        
      • Designed my 1 Bit ALU icon to be as large as the 16 bit ALU icon.
        (To make size constraints easy to plan for)
        

   2. 2 Bit ALU to 16 Bit ALU

      • Built my two bit ALU out of two ALU-1's.
        (with enough room for the ALU-16's wiring.)

        4 Bit ALU
        8 Bit ALU
        16 Bit ALU

3. PRAM/ROM

   1. I wanted a device that would allow me to code in a program to run by default, and/or to be able to gain manual control. Thus the PRAM/ROM was born. Looking back on it I would have just used a RAM as they're easy enough to modify the internal code.
      • PRAM/ROM
        
      • Top lines: are for manual input.
      • Left lines: the default running input lines. If no PROM or manual control is enable, it acts just like ram.
      • Center: Insert a PROM (11x16) here. Note the PROM address will start at 0x800
      • Right: 16 bit output.
      • By inputing a prom and setting the ram's address 0 to A800, I execute the following code.
        This tests my JMP, SDG, LDG, HLT, and JMI (although JMI has since been updated).
        The whole program consists of loading the data from [870] through [8A0] into the
        RAM, then JMP back to RAM[000] and execute.
        This tests a register shuffle and conditional jumping.

        6870 7000 6871 7001 6872 7002 6873 7003
        6874 7004 6875 7005 6876 7006 6877 7007
        6878 7008 6879 7009 687A 700A 687B 700B
        687C 700C 687D 700D 687E 700E 687F 700F
        6880 7010 6881 7011 6882 7012 6883 7013
        6884 7014 6885 7015 6886 7016 6887 7017
        6888 7018 6889 7019 688A 701A 688B 701B
        688C 701C 688D 701D 688E 701E 688F 701F
        6890 7020 6891 7021 6892 7022 6893 7023
        6894 7024 6895 7025 6896 7026 6897 7027
        6898 7028 6899 7029 689A 702A 689B 702B
        689C 702C 689D 702D 689E 702E 689F 702F
        68A0 7030 A000 XXXX XXXX XXXX XXXX XXXX
        XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
        A002 0000 F000 6010 7012 F000 6011 7010
        F000 6012 7011 F000 6010 9020 A028 FFFF
        0123 ABCD F000 F000 F000 F000 F000 F000
        F000 F000 F000 F000 F000 F000 F000 FFFF
        F000 F001 F002 F003 F004 F005 F006 F007
        F008 F009 F00A F00B F00C F00D F00E F00F
        A001 XXXX XXXX XXXX XXXX XXXX XXXX XXXX
        			

4. Encoder

   1. Just a little 3x8 bit encoder I threw together to make my clock output prettier.
      
      (ie: Instead of getting {0,1,2,4,8,0,1,2} from 2 hex displays,
      I now have 1 display that counts {0, ... 7})