Mark Rossen's Comp 212 WebLog

Lab 1

Jan 25, 7:30 PM

A simple start to the project.  We built a clock device that took a regular clock cycle and broke it down into 8 subcycles.  The tricky part was trying to figure out which flip flop could be used as a RUN device.   Fortunately Dr. Hasegawa allowed us to use a temporary device that allowed limitted functionality.  (i.e. the HALT line does not perform per specifications)  This was not an important issue, since it must be redesigned in later stages of the project.

Emailed to Dr. Hasegawa today, final circuit design: Lab1.cct

Lab 2

Feb 10, 7:30 PM

A two part, two week lab in which we built a skeletal processor.  This was a multi-stage process where we built one component on top of another.   Much of the design was laid out for us but the complexity of the processor still left plenty of room for error. 

  The first stage was to build a simple 12 bit register by combining 4 bit and 8 bit registers that already existed in the LogicWorks library. 

  Next we built a twelve bit Add1 adder that would be used to increment the program counter.  The Add1 would become an integral part of the PC, allowing the PC to increment itself instead of going to an external component.

We also built a 2x12 Multiplexor using 3 2x4 MUX's from the LogicWorks parts library.  This would also become part of the PC.  The 2x12 MUX would allow the PC to load from either its own add one component or from an external source.

  Now we combined all 3 previously built parts to create a fully functional program counter.  We also added a 4bit and an 8bit register to the output lines to act as a buffer.

Using our new program counter, another 12 bit register and the clock circuit that was built in Lab 1 the skeletal processor could be built.  The 12 bit register was used to create a memory address register (MAR) and required no modification.  The MAR and the PC were joined by a bus while the Load and Send inputs were connected to the clock circuit.  The PC was set to activate on the SC1 (2nd) clock cycle when it would internally increment its value and release this value onto the bus.  On the first clock cycle SC0 the MAR would be loaded from the bus taking on the new PC value.

Emailed to Dr. Hasegawa Feb 8, final circuit design: Processor.cct

Lab 3

Feb 18, 10:00 PM

The purpose of this lab was to add functionality to the base skeletal processor from Lab 2.  Four new parts were added.  A MBR (memory buffer register), a PROM,  IR (instruction register), and a MACH (4X16 Decoder).  When wired the goal was to load a 16 bit machine language instruction from the PROM (the address of the instruction coming from PC) into MBR and from there into an IR.   At this point the 4x16 decoder attached to the IR would decode the machine language instruction and the appropriate hardwired instruction would be executed.  For this lab the first and only instruction to be wired was HALT, which when executed would stop the clock cycle and thereby the processor.

The PROM was created through the LogicWorks4 Wizard making it little effort.  The MBR, IR, and MACH had to be created and their designs are shown below.

The new circuits were then wired together to produce the new skeletal processor with extended functionality.

Although there was a significant amount of work involved in this lab their were no serious difficulties.  Most bugs were easily traced to sloppy wiring or reversed pins.

Emailed to Dr. Hasegawa final circuit design as above.

Lab 4

March 1, 10:00 PM

In this lab we designed and built the ALU used by the CAPC processor.  Building what on first appearance seemed to be an extremely complex device proved to be more of an exercise in careful repetition.   The ALU was built in 5 stages, each component built using previous components, starting with a 1 bit ALU, then combining to create a 2 bit ALU, then a 4, 8  and finally a 16 BIT ALU.

The final 16-bit ALU is shown below.

Emailed to Dr. Hasegawa March 1, the above circuit.

Lab 5/6

March 7, 7:00 PM

The purpose of this experiment was to wire a new machine instruction into the skeletal processor.  The instruction LDG (load G register) would be the second hard wired instruction, HLT being the first.  This Lab would prove to be the most challenging yet in that it produced several bugs that were not easily diagnosed.

The first step was to create a 16-bit Buffer that would hold the address operand of a machine instruction in 12 bits and 0 in the remaining bits.  This would be attached to the bus and when the LDG instruction was executed would release the address operand onto the bus.  See part below:

A 16 bit register was added to the right side of the processor, this would be the G register.  With the parts in place the wiring of the LDG instruction was done.  Both the 16 bit (actually 12 + 4 0bits) buffer and the GREG were attached to the bus.  Wiring from subcycle 3 and 4 were attached to these circuits and the MACH to initiate and control the timing of the instruction.  Wiring was also implemented that would load the contents of the operand into MAR and release the contents of MBR onto the  bus at the appropriate time.  See completed circuit below: 

There were a number of problems with the circuit initially and many hours were spent debugging.  The most notable problem turned out to be a badly wired 12-bit Buffer.  There were also several timing related issues that had to be dealt with.

Emailed to Dr. Hasegawa March 8, the above circuit.

Lab 8

March 21, 3:00 PM

In this lab we wired one of the most heavily used machine language instructions SDG. (send G register)  The operations of the CAPC processor revolve around the G register making this one of the first instructions to be wired.  The SDG operation takes place over two clock subcycles, cycles 3 and 4.  In subcycle 3 the contents of the operand (representing an address) are loaded onto the bus and transferred to MAR, the memory address register.  In subcycle  4 this address value is used to reference the contents of RAM.  The contents of this address are loaded onto the bus and transferred into the G register completing the operation. 

The physical wiring for this operation is reasonably complex.  As with the past labs, attention to detail was the key.  Most bugs could be traced back to sloppy wiring and lack of care.  Perhaps because of past negative experiences, extra time and attention was given.  The result being few and minor bugs.  As with the last lab this one was debugged and running quite quickly.  Below is the resulting circuit.

The above circuit was emailed to Dr. Hasegawa March 21.

Lab 9

March 28, 10:00 PM

In this lab we finished creating the ALU started in lab 4 and wired it to our CAPC processor.  (the design is show in this weblog's Lab 4)  After wiring it in place we wired the ADD operation to take advantage of the new functionality supplied by the ALU.  This ADD operation was the most complex one we had yet wired.   It involved 5 clock subcycles (3-7) and required 2 registers to be loaded into the ALU before the ADD operation actually executed.  Although much of the wiring was similiar to past labs there was an increase in complexity.  Still no major bugs were encountered. 

The many multiple connections for this one instruction make it difficult to describe in words.   Below is a picture of the ADD operation's connections leaving the MACH and include it's immediate interactions with the ALU.

The final circuit above was emailed to Dr. Hasegawa

Lab 10?

March 5, 6:00 PM

This unofficial and final lab was used to wire the two jump instructions JMP and JMI.  The JMP instruction is a straightforward jump that changes the PC register to the contents of the operand.  It is straight forward in code and also very straightforward to wire.  The operation can be completed in one subcycle, the operand is released onto the bus and is immediately loaded into the PC register.  Code execution then carries on at the new address in PC.

The JNI (jump negative) is only slightly harder to wire.  In code the JNI command will jump (change the contents of PC) only when the contents of Greg are negative.   If Greg is negative it's bit 15 is activated, knowing this it is a simple matter to test that condition when the JNI instruction is encountered and jump accordingly.

Final Processor

Not really a complete processor but still quite functional.  There are now 7 instructions wired, NOP, HLT, LDG, SDG, ADD, JMP and JMI.  These are the most essential instructions and provide a surprising amount of functionality.  The final test of the processor was to add a series of numbers and store the sum in memory, which it did without difficulty.

Below is my final CAPC processor. 

CAPC Assembler

April 7, 11:00 PM

There's not much point in having a processor if you can't write programs for it!  Seeing as nobody had been there ahead of me, I decided to write the first CAPC Assembler.   Currently it is a simple 2 page Perl program, my first attempt at programming in that language. (probably the most cryptic code I have ever written)  It has had very little testing and has some limits to its functionality.  Anybody is welcome to use it, change it, whatever.

First test program:

; ;some test code to test jump negative (jmi) ;the first thing to be generated by my CAPC assembler! ; ; start: ldg numpos jmi jaddress ;should not jump yet ldg numneg jmi jaddress ;should jump now! hlt nop nop jaddress: ldg movefrom ;do something sdg moveto jmp start ;do it all again hlt ; ; movefrom=100 moveto=0 numpos=1 numneg=65000

The generated source output:

; ;some test code to test jump negative (jmi) ;the first thing to be generated by my CAPC assembler! ; ; 000 start 600E ldg numpos 001 9007 jmi jaddress ;should not jump yet 002 600B ldg numneg 003 9007 jmi jaddress ;should jump now! 004 0000 hlt 005 F000 nop 006 F000 nop 007 jaddress 600C ldg movefrom ;do something 008 700D sdg moveto 009 A000 jmp start ;do it all again 00A 0000 hlt ; ; 00B numneg = FDE8h 00C movefrom = 0064h 00D moveto = 0000h 00E numpos = 0001h

The hex codes it produces:

600E 9007 600B 9007 0000 F000 F000 600C 700D A000 0000 FDE8 0064 0000 0001

CAPC Assembler Pearl script: capcasm.pl

Another sample program: sample.txt