The Unique 4-bit IR Design

March 1, 2002

The original design of IR component is to receive a 16 bit value. It retains the upper 4-bits as the opcode, and it sends the lower 12-bits to MAR as the operand.

Normally, in the fetch cycle process, the following would occur:

T5F: IR <-- MBR

And then in the Execute cycle we would do the following:

T1E: MAR <-- IR[12..15]

We found this step, in conjunction with our memory design to be very inefficient. We wanted to eliminate the added step in T1E, but still accomplish the same task.

Our solution was to design a 4-bit IR that would receive its data during T5F. So now the updated fetch cycle would look as follows:

T5F: IR <-- MBR[12..15], MAR <-- MBR[0..11]

So MBR will send its data out to the bus, and MAR will grab the lower 11 bits, while IR grabs the upper 4 bits. The use of a 4-bit IR simplifies wiring and is easier to understand.

We now skip the step in T1E: MAR <-- IR[12..15]. With the extra time signal available, we can perform more in the execute cycle. We will also be less worried about signal delays and timing problems.

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