Development Schedule

Design files can be obtained by contacting our chief engineer. If you're the administrator, then you can take whatever files you want. We are also available to provide specialized consulting and can assist in any technical project.

Lab 1 - Designing clock circuit for CAPC
This unit produces 8 output signals, t0-t7, disjoint in the sense that one and only one output tx being positive at a time. One positive time interval is 10 time units, generated by the CLOCK device of Logic Works4

Lab 2 - Design and Implementation of Registers and Data Bus
For simplicity, our 16-bit processor CAPC has only one bus. In this experiment we design and implement two 2 bit generic registers and the bus. We will see how a Register-to-Register transfer works by using a clock signal generated by the CLOCK, designed and implemented in lab 1.

Lab 3 - RAM and Fetch Cycle
A 4K RAM unit is designed, based on a simulator provided by LogicWorks 4, and attached to the registers created in lab 2.

Lab 4 - Arithmetic and Logic Unit
We will be designing an ALU with 6 mode of operations, NOT, 2X, AND, OR, XOR, and SUM.

Lab 5 - Keyboard and Machine Instruction KTG
We will attach a Hexadecimal Keyboard port to our CAPC processor.

Lab 6 - Stored Program in PROM
We will write a simple program and store it in a PROM (Programmable Read Only Memory).

Lab 7 - Interrupt
The prime purpose of interrupt is to provide instantaneous communication between the processor, CAPC, and other interfaces which serve external devices. In this design of Interrupt circuits, we try to present a simple prototype, rather than a full-fledged Interrupt system.

Lab 8 - Control Unit - Adjusting Timer Signals
This is the final stage of our CAPC processor design. In this experiment we will look at fine tuning of CAPC, especially timing adjustment of its control unit. The Control Unit handles Fetch/Execute switch and timing.