Lab 1 - Designing Clock Circuit for CAPC

Design guidelines for lab 1.

January 25, 2002
This was a relatively straightforward design task. After some minor discussion in class, we decided on using a buffer system to simulate 4 unique stages of the clock. Our design was simple and flexible, easily allowing us to expand to any number of cycles desired.

February 1, 2002, Modification
Original design used output 4 signals. Analysis of the fetch cycle suggested we needed to increase the number of signals. In our operations, we may have to wait for data to settle down. Essentially, we want an operation to be fully completed before moving onto the next instruction. More signals allows us to lengthen the time we have for an instruction to complete. We added more buffers to our design to increase it to 8 signals.

February 15, 2002, Modification
Added a RUN input port to device. This gives us the option to halt the operation of the clock if we needed to. Control of this RUN input is from a HALT op code.

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Updates

Please see Lab 8 - Control Unit for further details on the modifications to the clock system. Timing and control of the fetch / execute cycle are discussed in greater detail there.