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Lab 2- Design and Implementation of Registers and Bus
Design guidelines for lab
2.
Feb 1, 2002
The goal was to design a general 16-bit register representing
MBR, IR, KTG, G, X, Y, and Z. After designing the 16-bit register,
the 12-bit register for MAR and PC will be produced by reducing
the 16-bit register. The 7474-chip consists of two D-type
flip-flops that can store one bit of data per flip-flop. We
used eight 7474 chips to produce the 16-bit storage. Port
In connectors were attached for D-inputs, clock, clear, preset,
and Port Out connectors to the Q-output. A buffer was attached
to the output of the clock. Then, the device was produced
and tested.
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February 8, 2002, Modification
The 16-bit register worked, but we realized there was a need
for an Enable switch. An AND gate was used. The one AND gate
input was for the output of the buffer with clock, and the
another AND gate output was for an Enable switch. The AND
gate output connected to the clock-inputs of the flip-flops.
The revised device was tested, and worked fine.
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March 8, 2002, Modification
There seemed to be conflicts between the buses. Another realization
occurred. When the 16-bit register was disabled, the clock receives
a zero, and the output of the register still outputted a value.
That is where the conflicts occur. We revised the 16-bit register
circuit by removing the AND gate between the buffer with clock
output. Next, we connected tri-state buffers between the Q-output
and the Port Out connectors. The enable on the tri-state buffers
became the main Enable switch for the register, when all connected
to one line. The device was made and tested to be fine. Testing
of a register showed to be promising, but when it was integrated
into CAPC, there was a long delay for the register output to
retrieve the value. We assumed the buffer had a preset delay,
so the buffers were initialized with zero delay to get around
the problem. |
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