Lab 3- Designing Memory Unit for CAPC

Design guidelines for lab 3 .

February 8, 2002
Initial design of RAM was tricky at first. We had problems with single mode emulation versus multiple word. For the initial design, we used single so we could test and understand a small scale component. Further work is required on this component. Coordinating RAM and bus depend a great deal on good and efficient design.

February 15, 2002 - Modification Entry
We realized that LogicWorks has built-in implementation of MBR register. Now we had two options. Either we use the MBR that is wired with the LogicWorks RAM, or we make a work-around and somehow include our own version of MBR.

We also saw the need for buffers to control the state of output because we found that we were getting different signal outputs. The following quote explains the use of buffers.

Hasegawa: "When you attach a device to the Bus, all output pins to the Bus MUST be 3-stated so that communication line is properly established between the destination device (receiving from the Bus) and the source device (sending to the Bus). Otherwise LogicWorks4 will flag "C" indicating multiple source devices present on the Bus."

February 28, 2002

Afterwards, we saw that single mode cannot work. We realize that for large-scale operations, multiple-word mode is the one that will work. This is a bug in LogicWorks.

March 5, 2002

We realized that our old design (v1.0) had inefficient pathways. Sending data to and from RAM required the use of MBR device way too much. In our new design, we decided to bypass this, and make direct connections to RAM. It is very efficient now. There are no DEMUX's in the system and timing issues are non-existant.

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Updates

Please see Lab 6 - PROM for further details on modifications to the memory system. There are many changes and tweaks that have to be performed. The memory unit is one of the most challenging aspects of our CAPC design.