Tech3 Midterm Report

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Brief Description of the Project:
Tech3 has been assigned to develop a 16-bit processor for CS212. We are studying the structure of a micro-processor in detail. The goal is to design and build a simple 16-bit processor using LogicWorks4 as the development tool. This goal will not be easy, and it will require a lot thought for the design and solving problems to come. The previous use of LogicWorks4 shows that it has some glitches, and those bugs can conflict or lengthen the time period of completion. Our diary will describe our achievements and difficulties. The complete product will be released in April 2002.

Summary of Diary:
Lab1:
In lab1, we developed a four-output clock unit by using a clock and three buffers for the outputs. Next, we had to expand that four-output into an eight-output clock. Finally, we added a halt switch. This lab was pretty simply and had no problems.

Lab2:
In lab2, a general 16-bit register had to be assembled for representing MBR, IR, KTG, G, X, Y, and Z. After producing the 16-bit register, the 12-bit register for MAR and PC will be produced by reducing the 16-bit register.

The 7474-chip consists of two D-type flip-flops that can store one bit of data per flip-flop. We used eight 7474 chips to produce the 16-bit storage. Port In connectors were attached for D-inputs, clock, clear, preset, and Port Out connectors to the Q-output. A buffer was attached to the output of the clock. Then, the device was produced and tested.

The 16-bit register worked, but we realized there was a need for an Enable switch. An AND gate was used. The one AND gate input was for the output of the buffer with clock, and the another AND gate output was for an Enable switch. The AND gate output connected to the clock-inputs of the flip-flops. The revised device was tested, and worked fine.

Later in the CAPC project, there seemed to be conflicts between the buses. Another realization occurred. When the 16-bit register was disabled, the clock receives a zero, and the output of the register still outputted a value. That is where the conflicts occur. We revised the 16-bit register circuit by removing the AND gate between the buffer with clock output. Next, we connected tri-state buffers between the Q-output and the Port Out connectors. The enable on the tri-state buffers became the main Enable switch for the register, when all connected to one line. The device was made and tested to be fine.

Testing of a register showed to be promising, but when it was integrated into CAPC, there was a long delay for the register output to retrieve the value. We assumed the buffer had a preset delay, so the buffers were initialized with zero delay to get around the problem.

Lab3:
In lab3, there were a few revisions to make it look cleaner. The PC, MAR, 12x16 RAM, MBR, and IR were connected respectively. A 32x16 MUX was produced from the 2x1 MUX in LogicWorks4. A 16x32 DeMUX was also made. After connection of these devices, problems were revealed. Conflicts appeared between buses. One of the causes was the register, which did not disable correctly. (As described in lab2.)
The other conflict was the DeMUX design. We used AND gates for our enable switch, but when disabled it still had an output value that conflicted between the bus lines. Similar to lab2 solution, we used tri-state buffers instead of AND gates.

After correcting that problem, the RAM functioned with a delay during output. Peter moved around that problem by using T2 connection to MBR to resolve the delay. However, just recently we were told that the RAM has a MBR delay embedded in memory. Deletion of the MBR was expected for the class, but Peter realized a better design where the MBR can exist without the interference of the RAM delay.

Next, there was a long delay output on the registers. We figured there was a preset delay in the buffers; that was corrected (as described in lab2).

The MUX suddenly stopped functioning, so Peter figure it was a glitch in LogicWorks4 design of the MUX. The MUX was redesigned and made from scratch.

Lab4:
In lab4, the construction of the Arithmetic and Logic Unit is done. This lab was pretty straightforward, and we did not encounter any problems. The ALU was tested and found nothing wrong so far.

Lab5:
In lab5, the making of a keyboard and machine instruction KTG was not difficult to understand and the wiring took some time. KTG data storage uses a general 16-bit register. The decoder sends the signal to a three-input AND gate, and then to the KTG register. The T7 from clock and fetch line respectively connects to the input of the three-input AND gate. So far we have not integrated the KTG into the CAPC yet.

Non-Specified Lab Achievements:
Attempted to test the write-ram feature, and encountered a conflict. When writing to RAM, the most recent write can be read from RAM, but the previous written data did not read correctly or have been lost. A combination of disabling and enabling of the write-RAM feature revealed this problem. After a long analysis of lab3 organization, it was apparent that the MBR was always enabled and the output data is always sent. The solution would be to enable MBR upon use, otherwise disabled.

Delay of the MUX and DeMUX made the RAM device very confusing, we were not able to debug our RAM device. Therefore we decide to try not using "common I/O" feature in our RAM unit. Thanks for the brilliant logic work program. This RAM unit causes great error and corrupts our whole design in MEMORY UNIT.

Luckily, we find out a way to separate input and output from RAM, and create a RAM without "common I/O" ourselves (We create it out of the one with "common I/O"). This new RAM unit works perfectly with register MAR and MBR. We are finally ready to put this unit to our CPU.